A comparator is used to compare two signals at its input terminals, and selectively controls its output to indicate which of the two input signals is larger. As comparators are not ideal circuit elements, every comparator will have an offset voltage. This offset voltage may be on the order of a few millivolts, but the presence of the offset of the comparator may distort the output of the device.
Comparators may be often used, for example, in a configuration of an analog to digital converter. An analog to digital converter (“ADC”) is used to convert an analog signal into a digital representation of the analog signal. The ADC typically samples the analog signal at periodic intervals and generates a digital value for each sample indicating the approximate magnitude of the sampled analog signal. One type of ADC uses a technique known as successive approximation recursively (“SAR”) to convert each analog input sample to a digital value. Another type of ADC is called a pipeline ADC. These converters typically include a plurality of stages, each of the stages having a digital to analog converter (“DAC”) and a flash ADC having many comparators to produce a digital value representing the magnitude of the analog input sample.
A limited offset may be acceptable for the comparator in the flash ADC of the pipeline ADC, but a pipeline ADC without a SHA will have an offset beyond the bounds of acceptability. An allocation can be made for the sampling bandwidth mismatch, but any offset of the comparator in the flash ADC if finite and may take up part of the allocation for the sampling bandwidth mismatch. Therefore, it is preferable to minimize the comparator offset and to distribute the majority of the allocation for the sampling bandwidth mismatch to the actual sample mismatch. This becomes problematic, because the comparator offset is not readily or easily removed in existing systems.
Previous efforts to address comparator offset have primarily focused on the implementation of analog elements to cancel any offset. However, these efforts have generally focused on the use of a high-gain preamplifier, which may add additional area to the integrated circuit and distort the overall gain of the circuit. Other efforts to address comparator offset have focused on using capacitors within comparator latch nodes to store and cancel the comparator offset. This is problematic, as it requires that the included capacitors touch the latch nodes which leads to the presence of parasitic capacitance in the converter. This parasitic capacitance is undesirable because it may slow down any converter in which the comparator is implemented.
Thus there remains a need in the art, for a system and method which allows for the correction of an offset in a general comparator on a per-comparator basis. There also remains a need in the art, for a system and method which allows for the removal of an offset for a comparator in the flash ADC of a pipeline ADC. There also remains a need in the art, for a system and method which allows for the calibration of the offset of a comparator in the flash ADC of a pipeline ADC in an efficient and controllable manner, particularly without affecting the converter speed or adding significant power to the pipeline ADC.